Espressif Systems /ESP32-P4 /SPI1 /SPI_MEM_CACHE_FCTRL

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Interpret as SPI_MEM_CACHE_FCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_MEM_CACHE_USR_ADDR_4BYTE)SPI_MEM_CACHE_USR_ADDR_4BYTE 0 (SPI_MEM_FDIN_DUAL)SPI_MEM_FDIN_DUAL 0 (SPI_MEM_FDOUT_DUAL)SPI_MEM_FDOUT_DUAL 0 (SPI_MEM_FADDR_DUAL)SPI_MEM_FADDR_DUAL 0 (SPI_MEM_FDIN_QUAD)SPI_MEM_FDIN_QUAD 0 (SPI_MEM_FDOUT_QUAD)SPI_MEM_FDOUT_QUAD 0 (SPI_MEM_FADDR_QUAD)SPI_MEM_FADDR_QUAD

Description

SPI1 bit mode control register.

Fields

SPI_MEM_CACHE_USR_ADDR_4BYTE

For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.

SPI_MEM_FDIN_DUAL

For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

SPI_MEM_FDOUT_DUAL

For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

SPI_MEM_FADDR_DUAL

For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

SPI_MEM_FDIN_QUAD

For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

SPI_MEM_FDOUT_QUAD

For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

SPI_MEM_FADDR_QUAD

For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

Links

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